Schedule of WARFP 2005

1:00PM

Introduction

1:05PM

Design Tool for Rapid System Prototyping on FPGAs [slides]
	Kerry Veenstra, Altera

1:15PM

UNUM: A General Microprocessor Framework Using Guarded Atomic Actions [slides]
	Nirav Dave, MIT
	Michael Pellauer, MIT

1:25PM

Prototyping Architectural Support for Program Rollback: An Application to Software Debugging [slides]
	Radu Teodorescu, UIUC
	Josep Torrellas, UIUC

1:35PM

Experiences Using FPGAs for Temperature-Aware Microarchitecture Research [slides]
	Siva Velusamy, U.Virginia
	Wei Huang, U.Virginia
	John Lach, U.Virginia
	Mircea Stan, U.Virginia
	Kevin Skadron, U.Virginia

1:45PM

Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA [slides]
	Taeweon Suh, Georgia Tech
	Hsien-Hsin S. Lee, Georgia Tech
	Sally A. McKee, Cornell
	Martin Schulz, Livermore

1:55PM

10 minute break

2:05PM

FAST: FPGA-based Acceleration of Simulator Timing Models [slides]
	Derek Chiou, U.Texas

2:15PM

Memory Subsystem Performance Evaluation with FPGA based Emulators [slides]
	Shih-Lien Lu, Intel
	Eriko Nurvitadhi, CMU
	Jumnit Hong, Oregon State
	Steen Larsen, Intel

2:25PM

A Parameterizable FPGA Prototype of a Vector-Thread Processor [slides]
	Jared Casper, MIT
	Ronny Krashinsky, MIT
	Christopher Batten, MIT
	Krste Asanovic, MIT

2:35PM

Full-Sysytem Architectural Exploration Sandbox [slides]
	Eriko Nurvitadhi, CMU
	James C. Hoe, CMU

2:45PM

FPGA-based Emulation Platforms at the Berkeley Wireless Research Center
	Bob Brodersen, Berkeley Wireless Research Center
	Nikolaus Bruels, Berkeley Wireless Research Center
	Chen Chang, Berkeley Wireless Research Center
	Kevin Camera, Berkeley Wireless Research Center
	Pierre-Yves Droz, Berkeley Wireless Research Center
	Hayden So, Berkeley Wireless Research Center
	John Wawrzynek, Berkeley Wireless Research Center
	Nan Zhou, Berkeley Wireless Research Center

2:55PM

ATLAS: A Scalable Emulator for Transactional Parallel Systems [slides]
	Christos Kozyrakis, Stanford
	Kunle Olukotun, Stanford

3:05PM

A Flexible Architecture for Simulation and Testing (FAST) Multiprocessor Systems [slides (pdf)] [slides (ppt)]
	John D. Davis, Stanford
	Lance Hammond, Stanford
	Kunle Olukotun, Stanford

3:15PM

Poster Session - See below

4:00PM - 5:00PM

Discussion

Posters

Reconfigurable Multiprocessor with Self-optimizing Self-assembling and Self-restoring Micro-architecture
	P.W. Chun, Ryerson U.
	V. Kirischian, Ryerson U.
	S. Zhelnakov, Ryerson U.
	L. Kirischian, Ryerson U.

Using an FPGA as a Prototyping Platform for Multi-core Processor Applications [poster]
	Christopher R. Clark, Georgia Tech
	Ripal Nathuji, Georgia Tech
	Hsien-Hsin S. Lee, Georgia Tech

Dusty Caches for Reducing Reference-Counting Memory Traffic
	Scott Friedman, Washington U.
	John Lockwood, Washington U.
	Ron Cytron, Washington U.
	Roger Chamberlain, Washington U.
	Jason Fritts, Washington U.

Semi-automatic Microarchitecture Configuration of Soft-Core Systems [poster]
	Shobana Padmanabhan, Washington U.
	John Lockwood, Washington U.
	Ron Cytron, Washington U.
	Roger Chamberlain, Washington U.
	Jason Fritts, Washington U.

FPGA Implementation of a Secure Microprocessor
	Takafumi Iwasa, Fukuoka U.
	Koji Inoue, PRESTO, Japan Science and Technology Agency

Development of Fuce Processor Emulator on Multiple FPGA Chips
	Masaaki Izumi, Kyushu U.
	Takanori Matsuzaki, Kyushu U.
	Satoshi Amamiya, Kyushu U.
	Makoto Amamiya, Kyushu U.

Toward A Common Emulation Infrastructure with Large-Scale FPGA [poster]
	Kenji Kise, U. Electro-Communications
	Takahiro Katagiri, U. Electro-Communications
	Hiroki Honda, U. Electro-Communications
	Toshitsugu Yuba, U. Electro-Communications

FPGA Co-Processors for Next-Generation Performance Monitoring Hardware
	Jeffrey Kulick, UAH
	Brett Boren, UAH

Exploring Shape-Aware Memory Through FPGA Prototyping
	L.R. Mullin, U. Albany
	R.M. Mattheyses, GE Global Research

An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding
	Yujia Jin, U.C. Berkeley
	Kaushik Ravindran, U.C. Berkeley
	Nadathur Satish, U.C. Berkeley
	Kurt Keutzer, U.C. Berkeley

Enhanced Processor Performance through APU Acceleration [poster]
	Peter Ryser, Xilinx

New Opportunities for Computer Architecture Research Using High-Density FPGAs and Design Tools [poster]
	Mazen A. R. Saghir, American U. of Beirut

Supporting Interdisiplinary Domain Specific Architecture Research with Reconfigurable Devices
	Timothy Sherwood, U.C. Santa Barbara
	Ryan Kastner, U.C. Santa Barbara
	Yan Meng, U.C. Santa Barbara
	Lin Tan, U.C. Santa Barbara
	Shreyas Prasad, U.C. Santa Barbara

Experiences with Multiprocessors Designs in Multiple FPGAs [poster]
	William Wu, White Eagle Systems Technology
	Dr. James Tobias, White Eagle Systems Technology
	Dr. Bob Uvacek, Toshiba

Design Considerations for FPGA-Based High-Performance CPUs
	James Ball, Altera
	Kerry Veenstra, Altera

SPREE: Microarchitectural Exploration on FPGAs [poster]
	Peter Yiannacouras, U. Toronto
	Jonathan Rose, U. Toronto
	J. Gregory Steffan, U. Toronto

Intra- and Inter-FPGA Progammable Multiprocessor Designs with Emphasis on Large-Scale Matrix Operations [poster]
	Sotirios G. Ziavras, NJIT