Alewife Baby Pictures, node board
Each Alewife node is packaged on a single PC board measuring 4.66 by
8.66 inches. The packaging of this prototype is very conservative,
using all through-hole technology and an 8-layer board. The node
layout was done by the APT group in the Information Sciences Institute (ISI) at
USC. Each node contains:
- A Sparcle integer CPU
-- a modification of a SPARC CPU built in collaboration with LSI Logic
and Sun Microsystems.
- An off-the-shelf SPARC FPU.
- A 64-kilobyte unified instruction/data cache (direct mapped,
16-byte lines).
- Eight (eventually 32) megabytes of DRAM.
- A Caltech EMRC routing chip
forming the local portion of a direct, two-dimensional mesh
interconnection network.
- A Communication and Memory Management
Unit (CMMU) on an LSI 300K gate array. The CMMU contains the cache
tags, the DRAM controller, the network interface and the state
machines which implement the hardware portion of the LimitLESS cache coherence
protocol.
Alewife node board
[512x768 image available, click for GIF
(218 kbytes) or JPG (88 kbytes)]
Alewife node board, three-quarters view
[512x768 image available, click for GIF
(260 kbytes) or JPG (102
kbytes)]
Alewife node board (with ruler for scale)
[512x768 image available, click for GIF
(216 kbytes) or JPG (90 kbytes)]
If these images are too bright or too dark when you display them, you
may want to read this short note about gamma
correction.
Back to Alewife baby pictures.
Back to Alewife.
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$Date: 1995/02/03 13:19:11 $
