Alewife Baby Pictures, CMMU die photo

The Communication and Memory Management Unit (CMMU) on each Alewife node:

holds the cache tags and implements the memory coherence protocol by synthesizing messages to other nodes (see references)
contains extra tag state for full/empty bits and handles all full/empty synchronization operations (see references)
contains mechanisms for rapid-context-switching (see references)
provides an efficient interface for sending and receiving both short and long messages (see references)
serves as a local memory controller (e.g., taking care of DRAM refresh, etc.)
provides a a wide array of hardware-based statistics, including cache miss ratios, average remote-access ratios, and locality histograms.

The Alewife CMMU (we call this the A-1000 CMMU) is implemented as a hybrid-gate array by LSI logic. This means that it is a mix of gate-array and standard-cell. This is evident from the die photo below: the regular structures are RAM cells, while the rest of the die is a "sea of gates".

The primary implementor of the CMMU was John Kubiatowicz. Compressed postscript for an extended abstract about the Alewife CMMU to be presented at Hot Chips '94 can be found here.

Alewife CMMU die photo (left) and rough floorplan (right).
[740x740 die photo available, click for GIF (418 kbytes) or JPG (149 kbytes)]
[664x840 floorplan available, click on image or here (GIF, 36 kbytes)]

If these images are too bright or too dark when you display them, you may want to read this short note about gamma correction.

Back to Alewife baby pictures.
Back to Alewife.

webmaster@cag.lcs.mit.edu $Date: 2009/08/13 18:56:52 $