Advanced Program for WARP2007

Saturday June 9, 2007
Session 1: Research Chips
Session Chair: Shih-Lien Lu, Intel

1:30pm-2:00pm
Prototyping the TRIPS Scalable Distributed Processing System
Stephen W. Keckler and Doug Burger
University of Texas at Austin

2:00pm-2:30pm
Prototyping the Scale Vector-Thread Processor
Ronny Krashinsky, Christopher Batten, Krste Asanovic
MIT

Session 2: FPGA Prototyping
Session Chair: Krste Asanovic, MIT/UC Berkeley

2:30pm-3:00pm
Building Various Levels of SOC Architecture Exploration Environments: System Level Simulator, Emulator and FPGA Prototype Board
Gi-Ho Park, Chang-Hoon Oh, Jong Wook Kwak , Hyun-Min Kyung, Jung-Bin Im, Sung Yong Cho, WooKyeong Jeong, Tae-Jin Kim, Sung-Bae Park,
Samsung Electronics

3:00pm-3:30pm
RiceNIC: Prototyping Network Interfaces
Jeffrey Shafer and Scott Rixner
Rice University

3:30pm-4:00pm Break
Session 3: FPGA Emulation
Session Chair: Mark Oskin, University of Washington

4:00pm-4:30pm
The Performance of FPGA Performance Models
Michael Pellauer, Joel Emer
MIT, Intel

4:30pm-5:00pm
Resource-Efficient FPGA Content-Addressable Memories
Kermin Fleming, Joel Emer
MIT, Intel

5:00pm-5:30pm
Virtualized Full-System Emulation of Multiprocessors using FPGAs
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
CMU

5:30pm-6:00pm
An Infrastructure for HW/SW Partitioning and Synthesis of Architectural Simulators
David A. Penry, Zhuo Ruan, Koy Rehme
Brigham Young University

6:00pm
Close