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Class Summary |
| AddBuffering |
After synch removal and conversion from the stream graph to the slice
graph, input slice nodes (joiners) or output slice nodes (splitter) may
not execute an integral number of times. |
| Address |
This class represents an unsigned 32-bit address in the
SpaceTime backend. |
| AnnealedGreedyLayout |
An experimental class that tries to optimize the data-reordering
stage of the greedy layout. |
| AnnealedLayout |
This class calculates the assignment of filters of slices to tiles of
the Raw chip by using simulated annealing. |
| BasicGenerateSteadyStateSchedule |
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| BasicSpaceTimeSchedule |
Collects initialization schedule, prime-pump schedule
and steady-state schedule in one place. |
| BCFile |
This class create the btl machine file for the application. |
| BenchChar |
Calculate and print some characteristics of the application. |
| BufferDRAMAssignment |
This class will assign the offchip-rotating buffers to DRAM banks of the
raw chip. |
| BufferedCommunication |
This class implements filter communication with a peek buffer. |
| CalculateParams |
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| CommunicateAddrs |
This class will generate code to allocate the off chip buffers on the necessary
tiles and then communicate each buffer's global address to the tiles that need
to know the address. |
| CompareSliceBNWork |
A Comparator for the work estimation of slices that compares slices
based on the amount of work in the bottleneck (the filter of the slice
that performs the most work). |
| CompCommRatio |
Calculate the computation to communication ratio. |
| ConvertCommunication |
This class will convert peek and pop statements into reads from a
buffer (an array). |
| ConvertCommunicationSimple |
This class will convert peek and pop statements into reads from a
buffer (an array). |
| ConvertPushesToMethCall |
This class will convert all of the pushes into function calls. |
| DirectCommunication |
If we can, this class will generate filter code that does not use a
peek buffer, so just read the values from the static network and write them to the
static network. |
| DRAMCommandDist |
Determine the number of read and write commands that each
dram has issued to it for a given schedule of slices. |
| DuplicateBottleneck |
This class holds various methods for extracting data parallelism
from the stream graph. |
| FileState |
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| GenerateComputeCode |
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| GeneratedVariables |
Class to hold the variables we generate during raw execution code
generated, it is passed around to various classes |
| GeneratePrimePumpSchedule |
This class operates on the SpaceTimeSchedule and generates the preloop
schedule for the partitioned stream graph. |
| GenerateSteadyStateSchedule |
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| GenerateSwitchCode |
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| GranularityAdjust |
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| GreedyBinPacking |
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| GreedyLayout |
This class calculates the assignment of filters to tiles using a
greedy bin packing heuristic. |
| InitSchedule |
This class generates the init schedule, the execution order as
given by the flow of the graph |
| InterSliceBuffer |
This class represents a buffer between two traces. |
| IntraSliceBuffer |
This class represents the buffer between the sink filter of a slice
and outputslicenode or between the inputslicenode and the source filter of a
slice. |
| IODevice |
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| LayoutDot |
This class generates a dot graph of the layout and for each tile the
schedule of filters that the tile runs. |
| Linear |
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| LinearFission |
This class will fiss a linear filter in a pipeline of smaller filters, where
each filter has a subset of the original weights. |
| LinearPreprocessor |
Replaces linear filters with two stage filters that
have and initWork that peeks 2(peek-pop) and pops (peek-pop)
Important for linear codegen |
| LogicalDramTileMapping |
This static class stores the logical mapping between tiles and drams that the
compiler uses to map buffers to drams. |
| MagicDram |
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| MagicDramInstruction |
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| MagicDramLoad |
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| MagicDramLoop |
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| MagicDramStore |
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| Makefile |
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| ManualDRAMPortAssignment |
This class asks the user to assign the input and output of each slice (trace) to a DRAM a
attached to the raw chip through an I/O port. |
| ManualSliceLayout |
Given a trace, ask the user where he/she wants it placed on
the raw chip. |
| MultiplySteadyState |
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| NumberGathering |
This class stores statistics needed to generate automatic performance
statistics on the raw simulator. |
| OffChipBuffer |
This abstract class represents a buffer in the partitioner slice graph. |
| POVRAYScheduleRep |
This class will create a 3D representation of the Space-Time
schedule to be rendered by the POVRAY rendering program installed
on the CAG farms. |
| RandomRouter |
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| RawBackEndFactory |
Factor out parts of RAW (at.dms.kjc.spacetime) back end that need matching types. |
| RawChip |
This class represents the raw chip to which we are compiling. |
| RawComputeCodeStore |
Repository for the compute code (SIR code that is converted to C
and mapped to the compute processor) for a tile. |
| RawComputeNode |
This abstract class represents a node of the Raw chip that
performs computation. |
| RawExecutionCode |
This abstract class defines an interface for filter code generators. |
| Rawify |
This class will rawify the SIR code and it creates the switch code. |
| RawProcElements |
The processing devices for RAW. |
| RawTile |
This class represents a raw tile on the raw chip with its compute
processor and its switch processor and the code that runs on each. |
| ReduceSJWidth |
This class will insert identity filters to reduce the width of
splitting and joining, so that it
It modifies the stream graph in place, adding edges and identities. |
| SafeFileReaderWriterPositions |
Separate FileReaders from splitters, FileWriters from joiners. |
| ScheduleModel |
This class models the calculated schedule and layout using the
work estimation for each filter of each slice. |
| SliceDotGraph |
This class will print out a dot graph representation of the slice (trace) graph either
before or after DRAM port assignment. |
| SmarterRouter |
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| SpaceTimeBackend |
The entry to the space time backend for raw. |
| SpaceTimeSchedule |
This class represents the space/time schedule for the application,
including both the steady state and the initialization stage. |
| StreamingDram |
This class represents a streaming dram (SDRAM) that can be attached
to a port of the raw chip. |
| StreamlinedDuplicate |
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| SwitchCodeStore |
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| TraceBufferSchedule |
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| TraceExtractor |
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| TraceIRtoC |
This class returns the c code (a string) for a given raw tile |
| Util |
A class with useful functions that span classes. |
| XYRouter |
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