In this class we will explore future directions for VLSI computer architecture, looking ahead to devices holding over one billion logic transistors. Students will discuss prior research and investigate new ideas with semester-long course projects. Topics may include: VLSI scaling trends and implications for architecture; techniques for obtaining parallelism at application, compiler, and hardware levels; future memory hierarchies including processor-in-memory structures; on-chip communication architectures; low-power and energy-exposed architectures; the future of I/O; reconfigurable computing; heterogeneous architectures.
We will meet twice a week for a mixture of lectures and class discussions of assigned readings. Grades will be based on class participation and a course project. All students are expected to read and digest all assigned reading and to articulate their views in a class discussion. Each student will be responsible for presenting one or more assigned papers and to lead a class discussion of the material. Students can perform course projects in groups and are encouraged to select topics that overlap with their own research. Each project will result in a conference-style 10 page paper and a 20-minute presentation. Enrollment may be limited.
|Assigned paper presentation||20%|