MHWU's Skew-free Signal Distribution Hacks


Skew-free Clock Distribution

The ability to distribute signals to all parts of a circuit with precisely controlled and known delays is essential in large, high-speed digital systems. We present a technique by which a signal driver can adjust the arrival time of the signal at the end of the wire using a pair of matched variable delay lines. We show how this idea can be implemented requiring no extra wiring, and how it can be extended to distribute signals skew-free to receivers along the signal run as well as the receiving end. We demonstrate how this scheme can be implemented as part of the pad and scan logic of a VLSI chip.

Eliminating Non-uniformities in Signal Buffer and Wires

Non-uniformities in buffer delays and wire lengths introduce skew in clock distribution trees. Previous techniques exist for eliminating skew introduced by each of these causes, not both. This method uses a pair of matched variable delay lines to eliminate skew caused both by differing buffer delays and wire lengths.


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Henry M. Wu
mhwu@zurich.ai.mit.edu
NE43-431
545 Technology Square
Cambridge, MA 02139
(617) 253-0290
no