Duane S. Boning

Duane Boning is an Assistant Professor of Electrical Engineering in the Electrical Engineering and Computer Science Department at MIT. He is affiliated with the Microsystems Technology Laboratories.

Research Interests

Duane's research interests include semiconductor process control, statistical metrology, process synthesis, tools and frameworks for process and device design, and the computer integrated manufacturing of integrated circuits.

Teaching

Duane is teaching recitation sections in 6.011, Communications, Control, and Signal Processing, during the Fall Term 1995. In the Spring Term 1995, he taught recitations in 6.001, a core undergraduate course in the Structure and Interpretation of Computer Programs.

Research Projects

Information Networking for Semiconductor Research
- Keeper of the Semiconductor Subway
- Distributed Design and Fabrication group in the MIT Computer-Aided Prototyping of Advanced Microsystems Project.
- National Research Enterprise with Stanford University. See a recent MIT/Stanford Semiconductor World-Wide-Web Demonstration held in August, 1995.
- World Wide Web interfaces to university fabrication facilities database, MTL, CAFE
- Semiconductor Process Representation
Semiconductor Process Control
- Plasma etch endpoint via interferometric imaging
- Real time control of plasma etch uniformity
- Plasma etch diagnosis via analysis of in-situ sensor data
- Run by Run Control algorithms, server implementation, user interface, and integration with CAFE
- Neural network approaches to run by run control; sampling/training strategies for semiconductor process modeling
- SPC charts for CAFE
- Real time control of silicon epitaxy growth rate
Statistical Metrology
- Statistical metrology of interlevel dielectric thickness
- Study of intra-die polysilicon critical dimension variation

Research Programs

Prof. Boning is associated with the following research programs:

Computer-Aided Prototyping of Advanced Microsystems
Computer Integrated Design and Manufacture Project
MIT Leaders for Manufacturing - Research Group 4 - Reduction in Variation
MIT Leaders for Manufacturing - Research Group 5 - Manufacturing Systems

Students (Advisor/Co-Advisor)

Todd Barrett (M.S., LFM)
Rajesh Divecha (M.Eng.)
Aaron Gower (M.S./Ph.D)
Byungho Han (M.S., LFM)
Minh Le (M.S./Ph.D.)
William Moyne (Ph.D.)
Dennis Ouma (Ph.D.)
Taber Smith (M.S./Ph.D.)
Brian Stine (Ph.D.)
David White (Ph.D.)
Ka Shun Wong (Ph.D.)
Chantal Wright (M.Eng.)
Kwong Yung (M.S.)

Recent Degrees (Advisor/Co-Advisor)

Arthur Altman (MS Mgmt/Eng - LFM 5/95)
Eric Chang (M.Eng. 1/96)
Jonathan Claman (M.Eng. 5/94)
Dawn Doherty Fitzgerald (MS Mgmt/Eng - LFM 5/94)
Nicole Love (MS 5/94)
Susan Kim (SB 5/94)
Daniel Maung (M.Eng.)
Sharon Price (SB 12/94)
Safroadu Yeboah-Amankwah (M.Eng. 5/94)

Address

Prof. Duane Boning
MIT, Room 39-567
Cambridge, MA 02139
Phone: 617 253-0931
FAX: 617 253-9606
Home: 617 643-6758
Email: boning@mtl.mit.edu
Sec: Scotti Fuller, 617 253-4657

Selected Publications

D. Boning and P. Mozumder, ``DOE/Opt: A System for Design of Experiments, Response Surface Modeling, and Optimization using Process and Device Simulation'', accepted for publication, IEEE Trans. Semi. Manuf., Jan. 1994.

M. D. Giles, D. S. Boning, G. R. Chin, W. C. Dietrich, M. S. Karasick, M. E. Law, P. K. Mozumder, L. R. Nackman, V. T. Rajan, D. M. H. Walker, R. H. Wang, and A. S. Wong, ``Semiconductor Wafer Representation for TCAD'', IEEE Trans. Computer Aided Design, Jan. 1994.

K. Gopalarao, P. Mozumder, and D. Boning, ``An Integrated Technology CAD System for Process and Device Designers'', IEEE Trans. VLSI Systems, pp. 482-490, Dec. 1993.

D. Durbeck, J.-H. Chern, and D. S. Boning, ``A System for Semiconductor Process Specification'', IEEE Trans. Semi. Manuf., pp. 297-305, Nov. 1993.

D. Boning, S. Ha, and E. Sachs, ``On-Line Control of Uniformity in Single-Wafer Plasma Etch Processes'', Extended Abstracts, TechCon '93, pp. 19-21, Semiconductor Research Corporation, Atlanta, GA, Sept. 1993.

D. S. Boning, M. B. McIlrath, P. Penfield, Jr., and E. M. Sachs, ``A General Semiconductor Process Modeling Framework'', IEEE Trans. Semi. Manuf., pp. 266-280, Nov. 1992. (postscript)

M. B. McIlrath, D. E. Troxel, D. S. Boning, M. L. Heytens, and P. Penfield, Jr., ``CAFE - The MIT Computer-Aided Fabrication Environment,'' IEEE Trans. on Comp., Hybrids, and Manuf. Tech., pp. 353-360, June 1992.

Biography

Duane S. Boning received the S.B. degrees in electrical engineering and in computer science in 1984, and the S.M. and Ph.D. degrees in electrical engineering in 1986 and 1991, respectively, all from the Massachusetts Institute of Technology. He was an NSF Fellow from 1984 to 1989, and an Intel Graduate Fellow in 1990. From 1991 to 1993 he was a Member Technical Staff at the Texas Instruments Semiconductor Process and Design Center in Dallas, Texas, where he worked on semiconductor process representation, process/device simulation tool integration, and statistical modeling and optimization.

Dr. Boning is an Associate Editor for the IEEE Transactions on Semiconductor Manufacturing, and has served as chairman of the CFI/Technology CAD Framework Semiconductor Process Representation Working Group. He is a member of the IEEE, Eta Kappa Nu, Tau Beta Pi, Sigma Xi, and the Association of Computing Machinery.