Raw Fabric
Prototype +  real world experience, fast
+  practical apps
-  static configuration
# tiles, I/O & memory ratio
Simulator - “magic”, slow simulation speed
+ scalability exploration
  (64 tiles is feasible in 90nm)
  lots of flexibility in
  I/O and memory experimentation
Exploration Avenues
for External Users
Then, we cut the silicon up into an array of 16 identical, programmable tiles.
Now, notice that blue line. That is the distance that signal can travel over a wire in a single cycle.
The width of a tile should be slightly less than this, so that we can go through a small amount of logic
and all the way across a tile in a single cycle.
By construction, we know that the longest wire in the system is no longer than the length or width of a tile.