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# tiles, I/O & memory ratio
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Then, we cut the silicon up into an array of 16 identical, programmable tiles.
Now, notice that blue line. That is the distance that signal can travel over a wire in a single cycle.
The width of a tile should be slightly less than this, so that we can go through a small amount of logic
and all the way across a tile in a single cycle.
By construction, we know that the longest wire in the system is no longer than the length or width of a tile.