Bnea
bnea   $2,$3, addr
branch not equal, meanwhile, add SPR BR_INCR
 minor tweak reduces some loop overheads by %50
 tagswi $0,$5, 3
 tagswi $0,$5, 2
 tagswi $0,$5, 1
 tagswi $0,$5, 0
 li   $4, kCacheSize - (kCacheLineSize << 2)
mtsri  BR_INCR, (kCacheLineSize << 2)
bnea+  $5, $4, ___cache_invalidate_loop
___cache_invalidate_loop:
li   $5, 0
BR_INCR is callee-saved
On the left is a zoomed-in photograph of the Raw tile, on the right is the standard cells placement. You can look at the proceedings
to identify different parts; but in particular, notice that you can see the 256 network wires on the upper left and right sides of the chip.
You can also kind of see them on the top and bottom a little bit. The white regions on the standard cell layout are where the network
wires pass through. You can also see the Rams, the very dark regions on the chip; the fuses for the rams (the white regions), and many
other details.