Data Cache
Data Cache
32KB per tile, 2-way set associative
allocate-on-write, write-back
tile caches are not coherent
- user manages coherence
Extensive collection of cache management instrs
for coherence management
•   tag-index-based for wide address range ops
•   address-based for short ranges
On the left is a zoomed-in photograph of the Raw tile, on the right is the standard cells placement. You can look at the proceedings
to identify different parts; but in particular, notice that you can see the 256 network wires on the upper left and right sides of the chip.
You can also kind of see them on the top and bottom a little bit. The white regions on the standard cell layout are where the network
wires pass through. You can also see the Rams, the very dark regions on the chip; the fuses for the rams (the white regions), and many
other details.