Branches & Divides
1 branch per cycle
no delay slots
static branch prediction bit   (e.g., bne+ bne-)
3 cycle mispredict penalty
Integer Divide 42 cycles
Floating Point Divide 12 cycles
The only non-pipelined instructions in the ISA.
Uses FD and HI/LO registers with full/empty bits.
Proc, IntDiv, FPDiv State Machines run independently
Processor will only stall if you read MFFD, MFLO, MFHI
before dividers have finished.
On the left is a zoomed-in photograph of the Raw tile, on the right is the standard cells placement. You can look at the proceedings
to identify different parts; but in particular, notice that you can see the 256 network wires on the upper left and right sides of the chip.
You can also kind of see them on the top and bottom a little bit. The white regions on the standard cell layout are where the network
wires pass through. You can also see the Rams, the very dark regions on the chip; the fuses for the rams (the white regions), and many
other details.