18.2 mm x 18.2 mm
16 Flops/ops per cycle
208 Operand Routes / cycle
2048 KB L1 SRAM
1657 Pin CCGA Package
1080 HSTL core-speed signal I/O
Raw ASIC
IBM SA-27E .15u 6L Cu
3.6 Peak GFLOPS (without FMAC)
230 Gb/s on-chip bisection bandwidth
201 Gb/s off-chip I/O bandwidth
@ 225 MHz Worst Case
(Temp, Vdd, process):