Raw’s I/O and Memory System
Raw
chipset
DRAM
DRAM
DRAM
DRAM
Text Box: DRAM
DRAM
DRAM
DRAM
PCI x 2
PCI x 2
DRAM
D/A
Routes on any network off the edge of the chip appear on the pins.
14 7.2 Gb/s channels
(201 Gb/s @ 225 Mhz)
Direct connection
of computation to
I/O and DRAM
Streams
Now that I’ve shown how we expose the wire resources, let me show you how we expose the pins.
It’s pretty simple. Routes off the edge of the chip are multiplexed down onto the pins. This gives
us 14 7.2 Gb/s channels, for a total of 201 Gb/s of bandwidth in and out of the chip.

We can hook up things like PCI buses, DRAMS and antennaes to these I/O ports. In fact, the problem
has been finding I/O devices that can come even close to saturating a channel.

Now, anyone can put a bunch of pins on a chip and get bandwidth. The key is that an tile can toggle an data pin just
by sending a message there. That means that we have a mechanism for directly controlling the I/O resources of the chip.
This contrasts with a conventional microprocessor, where it uses all of the pins solely to slosh cache lines back and forth.