The Raw Architecture: A Concrete Perspective

The Raw Tile

8 stage 32b

MIPS-style

single-issue

in-order compute

processor

Tile

4-stage 32b

pipelined FPU

32 KB DCache

32 KB IMem

Routers and wires for three

on-chip mesh networks


	Let’s look at what’s inside a tile. A tile is not a wimpy thing. It’s got an 8 stage 32b MIPS-style single-issue
	in-order compute processor,
	a 32 KB instruction memory, a 32 KB data cache, and a 4-stage single-precision pipelined floating point unit.
	Of course, we want to have the tiles work together and do useful work, so we’re also going to have a network
	interface and the routers and wires.