problem nodeXedge unrolled spec. gates vcycles fpgas speed speedup /FPGA /node g/F g/node v/f ------------------------------------------------------------------------------------------------------------------ add-small 16X 64 0.11 0.04 44254 14 14 111.6khz 4.46X 0.32 0.28 3161 2766 1.0 mult-medium 16X 64 0.18 0.16 155998 18 36 86.8 13.89X 0.39 0.87 4333 9750 0.5 mult-large 32X 127 0.81 0.68 310336 21 90 37.2 25.31X 0.28 0.79 3448 9698 0.23 add-mesh 64X 224 1.56 1.32 158989 16 46 24.4 32.31X 0.70 0.50 3456 2484 0.35 add-medium 64X 256 1.73 1.52 180712 22 56 17.7 26.90X 0.48 0.42 3227 2824 0.39 add-mlarge 128X 515 6.70 12.95 366156 32 118 6.1 40.87X 0.35 0.32 3103 2861 0.27 add-large 256X1140 40.00 77.50 814367 73 261 1.3 52.00X 0.20 0.20 3120 3181 0.28 and-medium 512X2051 138.51 185.35 186812 17 48 2.87 397.83X 8.29 0.78 3892 364 0.35 add-xlarge 384X1535 88.00 168.50 structure areas: edge node-0 node-1 node-2 node-3 node-4 node-5 node-6 node-7 node-8 add-medium 351 235 349 481 600 715 816 948 1062 1180 223 63 177 309 428 543 644 776 890 1008 128 172 172 172 172 172 172 172 172 172 and-medium 59 0 88 92 97 106 105 110 118 51 0 47 51 56 65 64 69 77 8 0 41 41 41 41 41 41 41 mult-large 1651 0 333 465 566 698 813 930 1045 1523 0 172 304 405 537 652 769 884 128 0 161 161 161 161 161 161 161 mult-medium 1648 0 328 460 561 693 808 925 520 0 167 299 400 532 647 764 128 0 161 161 161 161 161 161