IKOS VirtuaLogic Interface to SLIC EB-1 SBus Card

Directory Contents

Introduction from SLIC documentation:

"Dawn VME Products' SLIC EB-1 is a kit for prototyping hardware and software which provides a total solution for developing new SBus applications or porting existing applications from a different bus architecture. The kit centers around the Motoral MC92005 (a.k.a. SLIC) which is a complete SBus slave interface in a single chip."

"The MC92005's PBus is an asnychronous programmable private bus, whose signals and timing can be dynamically redefined, allowing it to interface to a wide variety of commercially-available peripheral chips."

MIT-RAW setup:

The external I/Os of an IKOS "Hermes" VirtuaLogic Emulation System are connected to the PBus interface of a SLIC card located in the host SPARC workstation. This directory contains the following:

• Software driver code in a sub-directory.
• Verilog code (interface.v system.v) which implements the VLE side of the interface
• Synopsys scripts (interface.syn system.syn) to synthesis this code into an IKOS-supplied target library
• Clock and pod files that describe the current configuration in our lab

The current interface is somewhat conservative in communicating between the synchronous clocking of the VLE system and the asynchronous PBus. Without taking advantage of any knowledge of the internal operations of the virtualization and high speed "virtual wires" clock in the VLE, and while sticking to a single edge clocking scheme, the interface has 2 cycle reads and writes

Because of its simplicity, the interface itself typical creates a critical path within the emulator of only 8 virtual cycles, so we do not expect it to be on the critical path of large designs.