#------------------------------------------------------------------------------
# $Header: /projects/raw/cvsroot/benchmark/suites/life/src/Makefile.in,v 1.7 1997/08/10 04:05:45 jbabb Exp $
#
# RAW Benchmark Suite Makefile for Life
#
# Authors: Rajeev Kumar Barua      (barua@lcs.mit.edu)
#          Jonathan Babb           (jbabb@lcs.mit.edu)
#
# Copyright @ 1997 MIT Laboratory for Computer Science, Cambridge, MA 02129
#------------------------------------------------------------------------------

# benchmark name:
BENCHNAME = Life

# parameterized benchmark versions to generate:
BENCHMARKS = \
	032_1_64_scan.v  \
	032_6_64_scan.v  \
	064_16_64_scan.v \
	096_16_64_scan.v \
	64_64_64_scan.v

# identify smallest benchmark version:
BENCHSMALL = 032_1_64_scan.v

# benchmarks to check before distribution:
BENCHCHECK = \
	032_1_64_scan.v  \
	032_6_64_scan.v

# generate program files:
GENERATE_FILES = ../src/generate.c

# driver program files:
DRIVER_FILES = ../src/driver.c

# verilog library program file:
LIBRARY_FILE   = ../src/library.v

# FPGA place and route hosts file:
HOSTS_FILE    = ../../../include/mit.hosts

# system architecture:
SYSTEM_ARCH   = raw

# maximum number of VirtuaLogic boards to use (1-6):
MAX_BOARDS    = 5

#speed of virtuaLogic emulator (1-8)
VLE_SPEED     = 7

# include directory:
INCLUDE_DIR   = ../../../include

# standard Makefile:
include $(INCLUDE_DIR)/$(SYSTEM_ARCH).make

# additional local things to make:
include ../src/Makefile.local
