Testchip Tool-Flow Tutorial

Current version:
Installed by:	Seongmoo Heo

The testchip tool-flow of Assam group for 0.18um TSMC process was originally developed by Albert Ma. This tutorial is based on his "Design Flow" presentation slides. In this example, I build a testchip called HEOMOO3. HEOMOO3 has two datapaths: one is connected to VDDdut supply and the other to VDDdut2. The one connected to VDDdut2 can be deactived through sleep transistors and an external sleep signal. HEOMOO3 uses the same pad-ring structure as ATC0 and has a custom-made datapaths and synthesized control logic gates. HEOMOO3 has 5 external input pins, 8 external output pins, 1 clock pin, and the rest of pins are power (2 special DUT power poins) and ground pins. The tutorial can be found at /home/bits6/heomoo/heomoo3chip/ which we assume as the home directory for this tutorial. It has subdirectories such as abstract, cds, design, mentor, pks, pm, se, and simulation.

abstract generates geometry/antenna libraries for custom-cells. cds includes Cadence custom-cell schematics and layouts, design has non-Cadence custom-cell source files CDL, floorplan, GDS, custom-made libraries, and verilog files), extracted netlists, and simulator binary files. mentor is used for DRC and LVS verification and RC extraction. pks does synthesis and placement. pm generates timing libraries. se does routing. simulation runs circuit-level simulation.

*NOTE: if OS is not mentioned separately, use Linux.

RTL Design Stage

Function: RTL design
Directory: ./design/verilog/
Output: verilog files (chip_nopads.v, inv_reg.v)

Function: RTL simulation and vector generation
Tool: vtoc, g++
Setup: setup vcs, setup vtoc
Directory: ./design/bin/
Input: all verilog files except for the top-level (chip.v) including pads, c++ wrapper file (chip_testbed.cc)
Output: executable simulator (atc2chip_csim) and VCD output (atc2chip_nopads_vtoc.vcd)
Viewer: gtkwave
Note: First, vtoc converts verilog files to c++. The converted c++ RTL files are wrapped with the c++ wrapper file and compiled to generate a simulator. The simulator generates inputs and outputs to the chip in VCD format.

Floorplanning Stage

Function: pad-ring generation
Tool: padgen.rb
Setup:
Directory: ./design/floor/
Input: pad description file (pads)
Output: pad-ring DEF file (padring.def) and pad-ring verilog file (atc2chip.v)
Note: The pad description file describes the number of pins and the size of the whole chip. atc2chip.v includes pads and atc2chip_nopad.v which has the actual design.

Function: floorplanning
Tool:
Setup:
Directory: ./design/floor/atc2chip/
Input:
Output: initial floorplan DEF file (padring.def)
Note: floorplan.def is the initial floorplan including power/ground rings and fixed (not placed) components. There is no floorplanning tool yet and the initial floorplanning should be done by directly typing in the locations of components, power/ground rings and stripes.

Custom-Cell Design Stage

Function: custom-cell schematic design
Tool: Cadence schematic editor (icfb)
Setup: setup ic
Example: ./cds
Input:
Output: Cadence custom-cell schematics
Note: Custom-cell schematics are located under heomoo3chip library. VSS is used for a ground pin. Make sure that the bottom-left point of prBound is located to the zero point.

Function: custom-cell layout design
Tool: Cadence virtuoso (icfb)
Setup: setup ic
Directory: ./cds/
Input:
Output: Cadence custom-cell layout files (invheomoo)
Note: Custom-cell layouts are located under heomoo3chip library.

Function: custom-cell DRC verification
Tool: Mentor Graphics Calibre DRC
Setup: setup mentic
Directory: ./cds/mentor/drc/
Input: Cadence custom-cell layouts
Output: DRC results
Note: runset - ./cds/mentor/drc/runset, calibre setup for layout export - ./cds/streamout

Function: custom-cell LVS verification
Tool: Mentor Graphics Calibre LVS
Setup: setup mentic
Directory: ./cds/mentor/lvs/
Input: Cadence custom-cell layouts and schematics
Output: LVS results
Note: runset - ./cds/mentor/lvs/runset, calibre setup for layout export - ./cds/streamout, calibre setup for netlist export - ./cds/cdlout

Function: custom-cell stream library generation
Tool: Cadence pipo
Setup: setup ic
Directory: ./cds
Input: Cadence cell layout files
Output: custom-cell library GDS file (./design/gds/chiplib.gds)
Note: All custom-cell GDS files are wrapped inside a custom-cell library GDS file. Blocks only include top-level units
Modify: Makefile , streamout.il

Function: custom-cell CDL generation
Tool: Cadence pipo
Setup: setup ic
Directory: ./cds
Input: Cadence cell schematic files
Output: custom-cell CDL files (./cds/simulation/cds/*.cdl)
Modify: Makefile

Custom-Cell Library Generation Stage

Function: geometry/antenna library generation
Tool: Cadence abstract
Setup: setup soc
Directory: ./abstract/
Input: custom-cell library GDS file (./design/gds/chiplib.gds), technology file (tech.dpux)
Output: custom-cell geometry LEF file (chip.lef) and custom-cell antenna LEF file (chip-antenna.lef)
OS: Solaris
Note: LEF stands for Library Exchange Format for placement and route. Geometry LEF file has information on the cell size and pins.
Modify: Makefile, tech.dpux, gds.li, cellname.li

Function: custom-cell layout extraction
Tool: Mentor Graphics Calibre xRC
Setup: setup mentic
Directory: ./design/spice/
Input: custom-cell library GDS file (./design/gds/chiplib.gds)
Output: RC extracted custom-cell netlists
Note: Each cell in the chip lib GDS file is extracted separately.
Modify: Makefile

Function: path delay measurement
Tool: Synopsys pathmill
Setup: setup pm
Directory: ./pm/
Input: RC extracted custom-cell netlists (./design/spice/*.sp, *.sp.pex, *.sp.*.pxi), pathmill control files (cfg, char), netlists (./pm/*/netlist.sp)
Output: SLIBS (./pm/*/*.lut.slib)
Note: Make separate directories for each custom-made cells and link netlists. Libheader includes pathmilll information on pgram and laram.
Modify: Makefile, cfg, char, netlist.sp, libheader

Function: timing library generation
Tool: Cadence syn2tlf, libcompile
Setup: setup ic, setup spr
Directory: ./pm/
Input: SLIBS (./pm/*/*.lut.slib)
Output: custom-cell TLF file (chip.tlf) and custom-cell ALF file (chip.alf)
OS: Solaris
Note: TLF stands for Timing Library Format for placement and route and ALF is a binary version of TLF. Each RC extracted cell is run with pathmill and each result (.lut.slib) is combined into a timing library file (.lib) which is translated into two other chip timing library files (.tlf and .alf)
Modify: Makefile, libheader

SPR (Synthesis,Placement,Routing) Stage

Function: synthesis and placement
Tool: Cadence PKS
Setup: setup spr
Directory: ./pks/floorplan/
Input: pad-ring verilog file (./verilog/chip.v), custom-cell geometry LEF file (./design/lib/chip.lef), custom-cell ALF file (./design/lib/chip.alf), pad-ring DEF file (./design/floor/padring.def), floorplan DEF file (./design/floor/floorplan.def), standard-cell verilog files (./verilog/chip_nopads.v, inv_reg.v), standard-cell geometry/timing library files (LEF,TLF,ALF), pad geometry/timing library files (LEF,TLF,ALF)
Output: synthesized chip verilog (chip.v), placed chip DEF file (chip.def)
OS: Solaris
Note: Timing constraints are met and a balanced clock tree is generated at this stage. The synthesized chip verilog is not used at all in this tool flow
Modify: run.tcl, design.tcl

Function: routing
Tool: makespecial2.rb, Cadence SE/wroute
Setup: setup dsmse
Directory: ./se/
Input: SE init file (se.ini), placed chip DEF file (./pks/floorplan/chip.def), custom-cell geometry/antenna LEF files (./design/lib/chip.lef, ./design/lib/chip_antenna.lef), standard-cell geometry/antenna LEF files, pad geometry/antenna LEF file, GDS map file (gds2.map)
Output: top-level chip GDS file (./design/gds/chip.gds), placed and routed chip DEF file (./se/output/chip_routed.def)
OS: Solaris
Note: Before routing, makespecial2.rb changes supply and ground nets to special nets. Sroute adds filler cells, creates power/ground grids (metal 6 for vertical wires and metal 5 for horizontal wires), and connect power/ground pins to the power/ground rings. Metal 5 power/ground wires should go over the datapath cells. After sroute, wroute routes all the signals starting with clock signals. To connect DUTs with special DUT Vdds, makespecial.rb should be modified
Modify: run.mac, makespecial.rb

Merging Stage

Function: stream merging
Tool: gdsMerge
Setup:
Directory: ./design/gds/
Input: top-level chip GDS file (chip.gds), custom-cell library GDS file (chiplib.gds), standard-cell library GDS file, pad library GDS file
Output: chip GDS file (top.gds)
GDS Viewer: calibredrv (/home/bits6/heomoo/design/gds/layers.txt)
Note: This chip GDS file is the golden GDS file submitted to a foundry.

Function: CDL merging
Tool: def2cdl, mergecdl
Setup:
Directory: ./design/cdl/
Input: placed and routed chip DEF file (./se/output/chip_routed.def), custom-cell CDL files (./cds/simulation/cdl/*.cdl), standard-cell library CDL file, pad library CDL file
Output: chip CDL file (top.cdl)
OS: Solaris (def2cdl)
Note: Before merging, the placed and routed chip DEF file should be translated into a CDL file by def2cdl. The chip CDL file is the golden CDL and used for LVS.
Modify: head

Chip-level Verification Stage

Function: DRC/ANT verification
Tool: Mentor calibre DRC/ANT
Setup: setup mentic
Directory: ./mentor/drc/
Input: chip GDS file (./design/gds/top.gds), rule file (drc.svrf)
Output: DRC/ANT reports (DRC.rpt, ANT.rpt)
Viewer: calibre -rve drc_res.db

Function: LVS verification
Tool: Mentor calibre LVS
Setup: setup mentic
Directory: ./mentor/lvs/
Input: chip GDS file (./design/gds/top.gds), chip CDL file (./design/cdl/top.cdl), header cells (hcells), rule file (lvs.svrf)
Output: LVS report (lvs.rep)
Modify: hcells, lvs.svrf, head

Simulation Stage

Function: chip layout extraction
Tool: Mentor calibre xRC
Setup: setup mentic
Directory: ./mentor/rcx/
Input: chip GDS file (./design/gds/top.gds), rule file (rcx.svrf)
Output: RC extracted chip spice netlist (chip.sp)

Function: circuit simulation
Tool: Synopsys nanosim, vtran
Setup: setup ns
Directory: ./simulation/
Input: RC extracted chip spice netlist (./mentor/rcx/chip.sp), input vector (chip_nopads_vtoc.vcd), nanosim files (cfg, chip.cmd, chip.vec), vtran file (chip.vtran)
Output: nanosim output (nanosim.out)
Viewer: signalscan (setup ldv, only on Solaris)
Note: First, VCD format is translated to EPIC format using vtran. nanosim simulates the chip netlist and compares its own outputs with the simulator-generated outputs. Nanosim spice model: /home/cad/tsmc/18/spice_model_lo/log018.l, Hspice spice model: /home/cad/tsmc/18/spice_model/fp1/hspice/log018.l

Please report any problems/errors to cagvlsi@cag.lcs.mit.edu.