Boston Area Architecture Conference 2003

Boston Area Architecture Workshop (BARC-2003)

Cambridge Marriot, January 30, 2003

Advance Technical Program

8:45am: Introduction
9am - 9:30am: Keynote (Session Chair: Joel Emer)
The Transactional Manifesto: Toward a Low-Level API for Scalable Synchronization, Maurice Herlihy, Brown University Computer Science

9:30am - 10:30am: Security and Reliability (Session Chair: Dave Kaeli)
Secure Hardware Processors. G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, and Srinivas Devadas, MIT LCS
Mondriaan Memory Protection, Emmett Witchel and Krste Asanovic, MIT LCS
Checker Processor Design, Chris Weaver, Intel Corporation and Todd Austin, University of Michigan

10:30am - 11am: Break

11am - noon: Memory Systems, Simulation, and I/O (Session Chair: Iris Bahar)
The Alpha 21364 Memory System, Peter Bannon, Dave Webb, Brian Lilly, Maurice Steinman, HP
Bridging the Compiler-Simulator Gap, Eliot Moss and Charles (Chip) Weems, University of Massachusetts, Amherst
Profile-Guided Data Partitioning to Achieve High Performance I/O, Yijian Wang, David R. Kaeli, Northeastern University

Noon - 1:30pm: Buffet Lunch

1:30pm - 2:30pm: Processor Organization (Session Chair: Csaba A. Moritz)
Decoupled Systolic Computation on Tiled Microarchitectures, Henry Hoffmann, Volker Strumpen, Anant Agarwal, MIT LCS
The Vector-Thread Architecture, Ronny Krashinsky, Chris Batten, and Krste Asanovic, MIT LCS
Characterization and Evaluation of Hardware Loop Unrolling, Marcos de Alba, David Kaeli, Northeastern University

2:30pm - 3:00pm: Break

3:00pm - 4:00pm: Power (Session Chair: Saman Amarsinghe)
Power-Aware System on a Chip, Andrew Laffely, Jian Liang, Russell Tessier, Csaba Andras Moritz, Wayne Burleson, Electrical and Computer Engineering Department, University of Massachusetts, Amherst
Combining Static and Runtime IPC Predictions for Chip-wide Energy Efficiency, Saurabh Chheda, Osman, Unsal, Csaba Andras Moritz, University of Massachusetts, Amherst
Combining Software and Hardware Monitoring for Improved Power and Performance Tuning, Eric Chi, A. Michael Salem, R. Iris Bahar, Brown University and Richard Weiss, Hampshire College

4:00pm - 4:30pm: Break

4:30pm - 5:30pm: Compiler Technology (Session Chair: Pete Bannon)
Using the Compiler to Improve Cache Replacement Decisions, Zhenlin Wang, Kathryn S. McKinley*, Arnold L. Rosenberg, Charles C. Weems, University of Massachusetts, Amherst and *UT Austin
Compiler-Enabled Cache Management for Pointer-Intensive Programs, Yao Guo, Saurabh Chheda, Csaba Andras Moritz, University of Massachusetts, Amherst
Meta Optimization: Improving Compiler Heuristics with Machine Learning, Mark Stephenson, Una-May O'Reilly*, Martin Martin*, Saman Amarasinghe, MIT LCS and *MIT AI Lab

5:30pm - 5:40pm: Concluding Remarks