This is a partial list of papers written or co-authored by members of
the Alewife Group.
Publications are listed by topic:
Anant Agarwal,
Ricardo Bianchini,
David Chaiken,
Frederic T. Chong,
Kirk L. Johnson,
David Kranz,
John Kubiatowicz,
Beng-Hong Lim,
Ken Mackenzie,
and Donald Yeung.
The MIT Alewife Machine.
In IEEE Proceedings, 1999
(paper [pdf,
compressed postscript])
Anant Agarwal,
Ricardo Bianchini,
David Chaiken,
Kirk L. Johnson,
David Kranz,
John Kubiatowicz,
Beng-Hong Lim,
Ken Mackenzie,
and Donald Yeung.
The MIT Alewife Machine: Architecture and Performance.
In ISCA '95
(abstract,
paper [pdf,
compressed postscript])
Anant Agarwal.
A Retrospective on The MIT Alewife Machine: Architecture and Performance.
In 25 Years of ISCA, 1998.
(paper [pdf,
compressed postscript])
Frederic T. Chong,
Beng-Hong Lim,
Ricardo Bianchini,
John Kubiatowicz, and
Anant Agarwal.
Application Performance on the MIT Alewife Multiprocessor.
1996.
(paper [compressed postscript])
Donald Yeung, William J. Dally,
Anant Agarwal.
How to Choose the Grain Size of a Parallel Computer.
MIT-LCR-TR 739, February 1994.
(paper [pdf,
compressed postscript])
John Kubiatowicz,
David Chaiken, and
Anant Agarwal.
The Alewife CMMU: Addressing the Multiprocessor Communications Gap.
Extended Abstract for Hot Chips '94, August 1994.
(paper [pdf,
compressed postscript])
Anant Agarwal, David Chaiken, Kirk Johnson, David Kranz, John Kubiatowicz, Kiyoshi Kurihara, Beng-Hong Lim, Gino Maa, Dan Nussbaum. The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor. MIT/LCS Technical Memo 454, 1991. Also in Scalable Shared Memory Multiprocessors, Kluwer Academic Publishers, 1991. (abstract, paper [pdf, compressed postscript] )
Anant Agarwal.
Performance Tradeoffs in Multithreaded Processors.
IEEE Transactions on Parallel and Distributed Systems,
October 1992.
(paper [ postscript])
Kiyoshi Kurihara, David Chaiken,
and Anant Agarwal.
Latency Tolerance through Multithreading in Large-Scale Multiprocessors.
Proceedings International Symposium on Shared Memory Multiprocessing,
pages 91-101, April 1991.
(abstract,
paper [pdf,
compressed postscript])
Anant Agarwal,
John Kubiatowicz,
David Kranz,
Beng-Hong Lim,
Donald Yeung,
Godfrey D'Souza, and Mike Parkin. Sparcle: An Evolutionary
Processor Design for Large-Scale Multiprocessors. IEEE Micro,
pages 48-61, June 1993.
(abstract,
paper [pdf,
compressed
postscript])
John D. Kubiatowicz.
Closing the Window of Vulnerability in Multiphase Memory Transactions:
The Alewife Transaction Store. Master's thesis, Massachusetts Institute
of Technology, Department of Electrical Engineering and Computer Science,
February 1993. Also available as MIT/LCS Technical Report 594. Note
that this includes implementation details which are not included in the
paper (below).
(abstract,
thesis [pdf,
compressed
postscript])
John Kubiatowicz,
David Chaiken,
Anant Agarwal.
Closing the Window of Vulnerability in Multiphase Memory
Transactions. Proceedings of the Fifth International Conference
on Architectural Support for Programming Languages and Operating Systems
(ASPLOS V), pages 274-284, October 1992.
(abstract,
paper [pdf,
compressed postscript])
Vijayaraghavan Soundararajan and
Anant Agarwal.
Dribbling Registers: A Mechanism for Reducing Context Switch
Latency in Large-Scale Multiprocessors.
MIT/LCS Technical Memo TM-474.
(abstract,
paper [pdf,
compressed postscript])
David Lars Chaiken.
Cache Coherence Protocols for Large-Scale Multiprocessors. Master's
thesis, Massachusetts Institute of Technology, Department of Electrical
Engineering and Computer Science, September 1990. Also available as MIT/LCS
Technical Report 489.
(abstract,
paper [pdf,
compressed
postscript])
David Chaiken,
John Kubiatowicz,
Anant Agarwal.
LimitLESS Directories: A Scalable Cache Coherence Scheme. Proceedings
of the Fourth International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS IV), pages 224-234, April 1991.
(abstract,
paper [pdf,
compressed
postscript])
David Chaiken and
Anant Agarwal.
Software-Extended Coherent Shared Memory: Performance and Cost.
Proceedings of the 21st Annual Symposium on Computer Architecture,
pages 314-324, April 1994.
(abstract,
paper [pdf,
compressed
postscript])
David Chaiken.
Mechanisms and Interfaces for Software-Extended Coherent Shared Memory.
Ph.D. thesis, Massachusetts Institute of Technology, Department of Electrical
Engineering and Computer Science, September 1994. Also available as MIT/LCS
Technical Report 644.
(abstract,
thesis [pdf,
compressed
postscript])
Donald Yeung,
John Kubiatowicz,
and Anant Agarwal.
MGS: A Multigrain Shared Memory System. Proceedings
of the 23rd Annual International Symposium on Computer Architecture,
pages 45-56, May 1996.
(abstract,
paper [pdf,
compressed
postscript])
Donald Yeung
. Multigrain Shared Memory. Ph.D. thesis,
Massachusetts Institute of Technology, Department of Electrical
Engineering and Computer Science, February 1998.
(abstract,
thesis [compressed postscript])
Anant Agarwal
. Modeling Multiprogrammed Caches.
MIT/LCS TM-488, June 1993.
(paper [pdf, compressed postscript])
Kirk Johnson.
The Impact of Communication Locality on Large-Scale Multiprocessor Performance.
Proceedings of the 19th Annual International Symposium on Computer Architecture,
pages 392-402, May 1992.
(abstract,
paper [pdf,
compressed postscript])
John Kubiatowicz and
Anant Agarwal.
The Anatomy of a Message in the Alewife Multiprocessor.
Proceedings of the International Conference on Supercomputing (ICS) 1993, pages
195-206, July 1993.
(abstract,
paper [pdf,
compressed
postscript])
Frederic T. Chong,
Rajeev Barua,
Fredrik Dahlgren,
John D. Kubiatowicz,
and Anant Agarwal. The
Sensitivity of Communication Mechanisms to Bandwidth and Latency. Proceedings
of 4th Int'l Symposium on High Performance Computer Architecture(HPCA),
Las Vegas, NV, Feb 1-4, 1998.
(abstract,
paper [pdf,
compressed
postscript])
John
D. Kubiatowicz.
Integrated Shared-Memory and Message-Passing Communication in the Alewife Multiprocessor.
PhD thesis, Massachusetts Institute of Technology, Department of Electrical
Engineering and Computer Science, February 1998.
(abstract,
thesis [pdf,
gzip'ed postscript])
David Kranz,
Kirk Johnson,
Anant Agarwal,
John Kubiatowicz, and
Beng-Hong Lim.
Integrating Message-Passing and Shared-Memory: Early Experience.
Proceedings of the Fourth Symposium on Principles and Practices of Parallel Programming,
pages 54-63, May 1993.
(abstract,
paper [pdf,
compressed
postscript])
Beng-Hong Lim
and Anant Agarwal.
Waiting Algorithms for Synchronization in Large-Scale Multiprocessors.
ACM Transactions on Computer Systems, pages 253-294, August 1993.
Also available as MIT VLSI Memo 91-632.
(abstract,
paper [pdf,
compressed
postscript])
David Kranz,
Beng-Hong Lim,
Anant Agarwal
and Donald Yeung.
Low-Cost Support for Fine-Grain Synchronization in Multiprocessors.
Multithreaded Computer Architecture: A Summary of the State of the Art,
Kluwer Academic Publishers, 1994.
(abstract,
paper [pdf,
compressed
postscript])
Donald Yeung
and Anant Agarwal.
Experience with Fine-Grain Synchronization in MIMD Machines for Preconditioned
Conjugate Gradient.
Proceedings of the Fourth Symposium on Principles and Practices of Parallel
Programming, pages 187-197, May 1993.
(abstract,
paper [pdf,
compressed
postscript])
Anant Agarwal
and Mathews Cherian.
Adaptive Backoff Synchronization Techniques.
Proceedings of the 16th Annual International Symposium on Computer Architecture, June
1989, pages 396-406
(abstract,
paper [pdf])
Rajeev Barua,
David Kranz,
and Anant Agarwal.
Communication-Minimal Partitioning of Parallel Loops and Data Arrays
for Cache-Coherent Distributed-Memory Multiprocessors Languages
and Compilers for Parallel Computing, August 1996. Springer Verlag,
Berlin, Germany.
(abstract,
paper [pdf,
compressed
postscript])
Rajeev Barua,
David Kranz,
and Anant Agarwal.
Addressing Partitioned Arrays in Distributed Memory Multiprocessors
- the Software Virtual Memory Approach.
Proceedings of the MIT Student Workshop, Wellesley, MA, July 1995.
(abstract,
two-page
workshop version,
full paper [pdf,
compressed postscript])
Daniel S. Nussbaum. Run-Time Thread Management for Large-scale Multiprocessors.
Ph.D. Thesis, Massachusetts Institute of Technology, Department of Electrical
Engineering and Computer Science, September 1993. Also available as MIT/LCS
Technical Report 596.
(abstract,
thesis [pdf,
compressed
postscript])
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