Alewife Baby Pictures
This page is under construction.
(descriptive text goes here)
Compressed postsript for an extended abstract about the Alewife CMMU
to be presented at Hot Chips '94 can be found here.
Click on the image to see a
full-size version of this
picture (740x740 GIF, 418 kbytes).
Each Alewife node is packaged on a single PC board measuring 4.66 by
8.66 inches. The packaging of this prototype is very conservative,
using all through-hole technology and an 8-layer board. The node
layout and all chassis mechanical design were done by the APT group in
the Information Sciences Institute
(ISI) at USC. Each node
contains:
- A Sparcle integer CPU
-- a modification of a SPARC CPU built in collaboration with LSI Logic
and Sun Microsystems.
- An off-the-shelf SPARC FPU.
- A 64-kilobyte unified instruction/data cache (direct mapped,
16-byte lines).
- Eight (eventually 32) megabytes of DRAM.
- A Caltech EMRC routing chip
forming the local portion of a direct, two-dimensional mesh
interconnection network.
- A Communication and Memory Management
Unit (CMMU) on an LSI 300K gate array. The CMMU contains the cache
tags, the DRAM controller, the network interface and the state
machines which implement the hardware portion of the LimitLESS cache coherence
protocol.
Click on the image to see a full-size
version of this picture (989x586 GIF, 296 kbytes).
webmaster@cag.lcs.mit.edu,
24 May 1994
