The Scheme86 Architecture
I have designed and am currently building a computer that is optimized
for a microcoded interpreter for Scheme.
The native language of this computer is SCode, a tree-structured,
typed-pointer representation of Scheme. The memory system is built
with high speed RAM and offers low latency as well as high throughput.
Multiple execution units in the processor make it possible to finish
most complex operations in less than one memory cycle, thus allowing
efficient use of memory bandwidth. The processor provides hardware
support for tagged data objects and runtime type checking. This
computer is designed as a back-end processor to a Hewlett Packard
workstation which will handle bootstrapping and I/O operations. I will
discuss the motivation for such a machine, its architecture, why it is
expected to interpret Scheme efficiently, and the computer aided
design tools I have developed for building this computer.
The Scheme86 and the HP Precision Architectures represent very
different trends in computer processor design. The former uses wide
micro-instructions, parallel hardware, and a low latency memory
interface. The latter encourages pipelined implementation, and
visible interlocks in both control and memory operations. To compare
the merits of the two approaches, algorithms frequently encountered in
numerical and symbolic computation, e.g. garbage collection, arbitrary
precision integer arithmetic, pattern matching, and FFT, were
hand-coded for each architecture. Timings were done in simulators and
the results were examined and evaluated to determine the equivalent
computing power of each design in the presence of a fast memory
system. Based on these measurements conclusions were drawn as to which
aspects of each architecture are suitable for a high performance
computing engine.
Go back to mhwu's home page.
Henry M. Wu
mhwu@zurich.ai.mit.edu
NE43-431
545 Technology Square
Cambridge, MA 02139
(617) 253-0290