The 2nd International Workshop on Machine Learning for Software Hardware Co-Design (MLSH'21)
September 26'th, 2021
Virtual - In conjunction with PACT21
- Paper submission: August 27th (AOE), 2021
- Paper notification: September 10th, 2021
- Camera-ready: September 20th, 2021
- Workshop: September 26'th, 2021
As Machine Learning (ML) continues to permeate all areas of computing, software system designers and software stack developers are adopting ML solutions and designs to solve challenging problems presented in their areas; especially in areas like optimization and hardware design. ML is increasingly being used to solve a diverse set of problems such as the design of cost models, code optimization heuristics, efficient search space exploration, automatic optimization, and program synthesis. Designing accurate machine learning models, feature engineering, verification, and validation of obtained results and selecting and curating representative training data are all examples of challenging but important problems in this area that are actively being explored by a large community of researchers in industry and academia. This workshop provides a great venue for the international research community to share ideas and techniques to apply machine learning to system challenges with a focus on the software stack and hardware.
We will solicit papers on topics including, but not limited to, the following areas:
- ML for the software stack
- Heuristics and cost model construction.
- Optimization space exploration.
- Automatic code optimization.
- Bug detection.
- Program synthesis.
- Program and code representation.
- Important training paradigms.
- ML for hardware
- ML models for optimal configuration for FPGA.
- Load balancing between CPU and accelerators (e.g. GPUs, TPUs, etc).
- ML models to improve computer architecture design.
- Analysis and techniques to define meaningful representation (features) for compilers and hardware.
- Training data
- Exploring the availability or generation of efficient training data for compilers and hardware.
- Utilizing graph-based data for machine learning.
We invite both full-length research papers and short research papers.
The submitted paper should not exceed the page limit (8 pages for full-length and 4 pages for short papers) and should follow the IEEE conference proceedings templates.
The page limit applies to all content NOT including references, and there is no page limit for references.
The submission will be reviewed by at least three program committee members and should not have published in or under review for another venue. Accepted papers will be published in our online proceedings. Submit your paper using this link.
September 26th from 11am ET to 1:50pm ET (Eastern Time).
|11:05-11:35AM||Marco Minutoli (PNNL)
SODA: Agile Hardware Design for Specialized Systems.
|11:35 - 12:05PM||
Anup Das (Drexel University)
Intelligent Software for Intelligent Machines.
|12:05 - 12:15PM||Break.|
|12:15 - 12:45PM|| Massinissa Merouani (New York University Abu Dhabi)
A Deep Learning Based Cost Model for Automatic Code Optimization.
|12:45-1:15PM||Jordi Armengol-Estape (University of Edinburgh)
Learning C To X86 Translation: an Experiment in Neural Compilation.
|1:15 - 1:45PM||
Yundi Qian, Mircea Trofin (Google)
MLGO: Machine Learning Guided (Compiler) Optimization.
|1:45 - 1:50PM||Closing notes.|
How to Attend?
All the presentations will be virtual. To attend, please join the following Zoom Link (Meeting ID: 977 4123 9295, Passcode: 624270).