The Carbon research group is focused on research related to multicore architectures and software. We are a part of the Computer Science and Artificial Intelligence Lab at MIT.

This is a list of publications authored by members of the Carbon research group:

Operating Systems

  • Message Passing in a Factored OS,
    by Adam Belay, Anant Agarwal
    Masters Thesis, July 2011
    (pdf)
  • Distributed Parallel Network Stack for Multicore,
    by Charles Gruenwald, Nathan Beckmann, David Wentzlaff, Harshad Kasture, Jeff Ward, and Anant Agarwal NSDI Poster Session, March 2011
  • Fleets: Scalable Services in a Factored Operating System,
    by David Wentzlaff, Charles Gruenwald III, Nathan Beckmann, Adam Belay, Harshad Kasture, Kevin Modzelewski, Lamia Youseff, Jason E. Miller, and Anant Agarwal
    MIT CSAIL Tech Report 2011-012, March 2011
    (pdf)
  • An Operating System for Multicore and Clouds: Mechanisms and Implementation,
    by David Wentzlaff, Charles Gruenwald III, Nathan Beckmann, Kevin Modzelewski, Adam Belay, Lamia Youseff, Jason Miller, and Anant Agarwal
    ACM Symposium on Cloud Computing (SOCC), June 2010
    (pdf)
  • A Unified Operating System for Clouds and Manycore: fos,
    by David Wentzlaff, Charles Gruenwald III, Nathan Beckmann, Kevin Modzelewski, Adam Belay, Lamia Youseff, Jason Miller, and Anant Agarwal
    1st Workshop on Computer Architecture and Operating System co-design (CAOS), Jan 2010. (pdf)
  • Factored Operating Systems (fos): The Case for a Scalable Operating System for Multicores,
    by David Wentzlaff and Anant Agarwal.
    ACM SIGOPS Operating System Review (OSR), April 2009. (pdf)
  • The Case for a Factored Operating System (fos),
    by David Wentzlaff and Anant Agarwal.
    MIT CSAIL Technical Report, MIT-CSAIL-TR-2008-060, October 2008. (pdf)

Smart Data Structures

  • Smart Data Structures: An Online Machine Learning Approach to Multicore Data Structures, by Jonathan Eastep, David Wingate, and Anant Agarwal.
    8th IEEE/ACM International Conference on Autonomic Computing (ICAC’11), 2011. (pdf)
  • Smartlocks: Lock Acquisition Scheduling for Self-Aware Synchronization, by Jonathan Eastep, David Wingate, Marco D. Santambrogio and Anant Agarwal.
    7th IEEE/ACM International Conference on Autonomic Computing (ICAC’10), 2010. (pdf)
  • Smartlocks: Self-Aware Synchronization through Lock Acquisition Scheduling, by Jonathan Eastep, David Wingate, Marco D. Santambrogio and Anant Agarwal.
    MIT CSAIL Technical Report, MIT-CSAIL-TR-2009-055, November 2009. (pdf)

SEEC: A Framework for Self-Aware Computing

  • Control-theoretical CPU allocation: Design and Implementation with Feedback Control,
    byMartina Maggio, Henry Hoffmann, Anant Agarwal, and Alberto Leva.
    The 6th International Workshop on Feedback Control Implementation and Design in Computing Systems and Networks (FeBID 2011). (to appear)
  • Decision Making in Autonomic Computing Systems: Comparison of Approaches and Techniques,
    byMartina Maggio, Henry Hoffmann, Marco D. Santambrogio, Anant Agarwal, and Alberto Leva.
    The 8th IEEE/ACM International Conference on Autonomic Computing and Communications (ICAC 2011). (to appear)
  • A comparison of autonomic decision making techniques,
    byMartina Maggio, Henry Hoffmann, Marco D. Santambrogio, Anant Agarwal, and Alberto Leva.
    MIT CSAIL Technical Report, MIT-CSAIL-TR-2011-019
    , April 2011. (doi),
  • SEEC: A framework for self-aware management of multicore resources,
    by Henry Hoffmann, Martina Maggio, Marco D. Santambrogio, Alberto Leva, and Anant Agarwal.
    MIT CSAIL Technical Report, MIT-CSAIL-TR-2011-016
    , March 2011. (doi)
  • Dynamic knobs for responsive power-aware computing,
    by Henry Hoffmann, Stelios Sidiroglou, Michael Carbin, Sasa Misailovic, Anant Agarwal, Martin C. Rinard.
    16th international conference on architectural support for programming languages and operating systems
    (ASPLOS2011), March 2011. (doi)
  • Controlling software applications via resource allocation within the heartbeats framework,
    by Martina Maggio, Henry Hoffmann, Marco D. Santambrogio, Anant Agarwal, and Alberto Leva.
    49th IEEE Conference on Decision and Control (CDC2010),
    December 2010. (doi)
  • SEEC: A framework for self-aware computing,
    by Henry Hoffmann, Martina Maggio, Marco D. Santambrogio, Alberto Leva, and Anant Agarwal.
    MIT CSAIL Technical Report, MIT-CSAIL-TR-2010-049, October 2010
    . (doi)
  • Enabling technologies for self-aware adaptive systems,
    by
    Marco D. Santambrogio, Henry Hoffmann, Jonathan Eastep, Jason E. Miller, and Anant Agarwal.
    Conference on Adaptive Hardware and Systems (AHS), 2010 NASA/ESA, pp 149-156, June 2010. (doi)
  • Application Heartbeats: A Generic Interface for Specifying Program Performance and Goals in Autonomous Computing Environments,
    by
    Marco D. Santambrogio, Henry Hoffmann, Jonathan Eastep, Jason E. Miller, and Anant Agarwal.
    The 7th IEEE/ACM International Conference on Autonomic Computing and Communications (ICAC2010)
    , pp 79-88, June 2010. (doi)
  • Application Heartbeats for Software Performance and Health,
    by
    Henry Hoffmann, Jonathan Eastep, Marco D. Santambrogio, Jason E. Miller, and Anant Agarwal.
    15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming,
    pp.347-348, January 2010. (pdf)
  • Application Heartbeats: A Generic Interface for Expressing Performance Goals and Progress in Self-Tuning Systems,
    by Henry Hoffmann, Jonathan Eastep, Marco D. Santambrogio, Jason E. Miller, and Anant Agarwal.
    4th Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion (SMART’10),
    2009. (nay)
  • Application Heartbeats for Software Performance and Health,
    by
    Henry Hoffmann, Jonathan Eastep, Marco D. Santambrogio, Jason E. Miller, and Anant Agarwal.
    MIT CSAIL Technical Report,
    MIT-CSAIL-TR-2009-035, August 2009. (pdf)

Parallel Design Patterns

  • Selecting Spatiotemporal Patterns for Development of Parallel Applications,
    by Henry Hoffmann, Anant Agarwal, and Srinivas Devadas.
    IEEE Transactions on Parallel and Distributed Systems (to appear)
  • A pattern for efficient parallel computation on multicore processors with scalar operand networks,

    by Henry Hoffmann, Srinivas Devadas, and Anant Agarwal.
    Proceedings of the 2010 Workshop on Parallel Programming Patterns, March 2010. (doi)

  • Partitioning Strategies: Spatiotemporal Patterns of Program Decomposition,
    by Henry Hoffmann, Anant Agarwal, and Srinivas Devadas.
    Proceedings of the 21st IASTED Conference on Parallel and Distributed Computing and Systems,  November 2009 (link).
  • Partitioning Strategies for Concurrent Programming,
    by Henry Hoffmann, Anant Agarwal, and Srinivas Devadas.
    Proceedings of the 2009 Workshop on Parallel Programming Patterns,  June 2009 (link).

ATAC: A Manycore Processor with On-Chip Optical Network

  • ATAC: A 1000-Core Cache-Coherent Processor with On-Chip Optical Network by George Kurian, Jason Miller, James Psota, Jonathan Eastep, Jifeng Liu, Jurgen Michel, Lionel Kimerling, Anant Agarwal, in Proceedings of Parallel Architectures and Compilation Techniques (PACT), Sept 11-15, 2010. (pdf)
  • ATAC: Improving Performance and Programmability with On-Chip Optical Networks by James Psota, Jason Miller, George Kurian, Hank Hoffman, Nathan Beckmann, Jonathan Eastep and Anant Agarwal, in Proceedings of International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010. (pdf)
  • ATAC: A Manycore Processor with On-Chip Optical Network by Jason Miller, James Psota, George Kurian, Nathan Beckmann, Jonathan Eastep, Jifeng Liu, Mark Beals,
    Jurgen Michel, Lionel Kimerling, and Anant Agarwal. MIT CSAIL Technical Report, MIT-CSAIL-TR-2009-018, May 5, 2009. (pdf)
  • ATAC: All-to-All Computing Using On-Chip Optical Interconnects by James Psota, Jonathan Eastep, Jason Miller, Theodoros Konstantakopoulos, Michael Watts, Mark Beals, Jurgen Michel, Kim Kimerling, Anant Agarwal, in Boston Area Architecture (BARC), Jan 26, 2007 (pdf)

Simulation

  • Graphite: A Distributed Parallel Simulator for Multicores
    by Jason E. Miller, Harshad Kasture, George Kurian, Charles Gruenwald III, Nathan Beckmann, Christopher Celio, Jonathan Eastep and Anant Agarwal
    The 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Jan 2010. (pdf)

Raw Architecture, Prototype, Compiler, and Scalable Microprocessor Research

  • Baring it all to Software: Raw Machines,
    by Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal.
    IEEE Computer, September 1997, pp. 86-93. (pdf, postscript, compressed postscript)
  • Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,
    by Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal.
    Proceedings of International Symposium on Computer Architecture, June 2004. (pdf, ps)
  • Scalar Operand Networks: Design, Implementation, Analysis,
    by Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
    MIT/LCS Technical Memo LCS-TM-645, June 2004. In IEEE TPDS, 2005. (pdf, ps)
  • Scalar Operand Networks: On-chip Interconnect for ILP in Partitioned Architectures,
    by Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
    Proceedings of the International Symposium on High Performance Computer Architecture, February 2003. (pdf)
  • Software-based Instruction Caching for Embedded Processors,
    by Jason Miller and Anant Agarwal.
    Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), San Jose, CA, October 2006. (pdf, postscript, compressed postscript, bibtex)
  • Energy Scalability of On-Chip Interconnection Networks in Multicore Architectures,
    by Theodoros Konstantakopoulos, Jonathan Eastep, James Psota, and Anant Agarwal
    MIT CSAIL Technical Report, November, 2007 (pdf)
  • A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network
    by Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffmann, Paul Johnson, Walter Lee, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Saman Amarasinghe, and Anant Agarwal.
    Proceedings of the IEEE International Solid-State Circuits Conference, February 2003. (pdf)
  • The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs,
    by Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff,
    Fae Ghodrat, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jae-Wook Lee, Walter Lee,
    Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen
    Matt Frank, Saman Amarasinghe and Anant Agarwal.
    IEEE Micro, Mar/Apr 2002. (pdf),
  • SimpleFit: A Framework for Analyzing Design Trade-Offs in Raw Architectures,
    by Csaba Andras Moritz, Donald Yeung, and Anant Agarwal.
    IEEE Transactions on Parallel and Distributed Systems, Vol. 12, No. 7, July 2001. (pdf)
  • Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,
    by Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, and Saman Amarasinghe.
    Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, October 4-7, 1998. (pdf, postscript, compressed postscript)
  • Energy Characterization of a Tiled Architecture Processor with On-Chip Networks,
    by Jason Sungtae Kim, Michael Bedford Taylor, Jason Miller, and David Wentzlaff.
    International Symposium on Low Power Electronics and Design, August 2003. (pdf)
  • Compiler Support for Scalable and Efficient Memory Systems,
    by Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal.
    IEEE Transactions on Computers, Nov 2001. (pdf, postscript, compressed postscript)

Space-Time and Convergent Scheduling, Stream Compilation

  • Convergent Scheduling,
    by Walter Lee, Diego Puppin, Shane Swenson and Saman Amarasinghe.
    Proceedings of the 35th International Symposium on Microarchitecture, Istanbul, Turkey, November, 2002. (pdf, postscript)
  • Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,
    by Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, and Saman Amarasinghe.
    Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, October 4-7, 1998. (pdf, postscript, compressed postscript)
  • See also More Raw and Streamit Related Compiler Papers by the MIT Commit Group.

Raw Application Studies

  • A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-level Computation,
    by David Wentzlaff and Anant Agarwal.
    MIT/LCS Technical Report LCS-TR-944, April 2004 (pdf)
  • A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels,
  • by Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French
    Proceedings of the International Symposium on Computer Architecture, June 2003. (pdf)

Reconfigurable Compilation and Computing Research

  • Parallelizing Applications into Silicon,
  • (pdf, postscript, compressed postscript)
    by Jonathan Babb, Martin Rinard, Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, and Saman Amarasinghe.
    Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines ‘99 (FCCM ‘99), Napa Valley, CA, April 1999

  • The RAW Benchmark Suite: Computation Structures for General Purpose Computing,
  • (pdf, postscript, compressed postscript)
    by Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Taylor, Jang Kim, Srikrishna Devabhaktuni, and Anant Agarwal.
    This paper appears in IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, April 1997.

  • Solving graph problems with dynamic computation structures,
  • (pdf, postscript, compressed postscript)
    by Jonathan Babb, Matthew Frank, and Anant Agarwal.
    This paper appears in SPIE Photonics East: Reconfigurable Technology for Rapid Product Development & Computing, Boston, MA, November 1996.More related papers in Virtual Wires Documents.

Compiler-Managed Memory System Research

  • Software-based Instruction Caching for Embedded Processors,
    by Jason Miller and Anant Agarwal.
    Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), San Jose, CA, October 2006. (pdf, postscript, compressed postscript, bibtex)
  • Software Instruction Caching,
    by Jason E Miller.
    PhD Thesis, Massachusetts Institute of Technology, Cambridge, MA, June, 2007. (pdf, postscript, compressed postscript, bibtex)
  • SUDS: Primitive Mechanisms for Memory Dependence Speculation,
    by Matthew Frank, C. Andras Moritz, Benjamin Greenwald, Saman Amarasinghe, and Anant Agarwal.
    MIT/LCS Technical Memo LCS-TM-591, January 6, 1999. (pdf, postscript, compressed postscript)
  • Compiler Support for Scalable and Efficient Memory Systems,
    by Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal.
    IEEE Transactions on Computers, Nov 2001. (pdf, postscript, compressed postscript)
  • Maps: A Compiler-Managed memory system for Software-Exposed Architectures,
    (pdf, postscript, compressed postscript)
    by Rajeev Barua. PhD Thesis. MIT Laboratory for Computer Science. Jan 2000.
  • Maps: A Compiler-Managed Memory System for Raw Machines,
    (pdf, postscript, compressed postscript)
    by Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
    Proceedings of the Twenty-Sixth International Symposium on Computer Architecture (ISCA-26), Atlanta, GA, June, 1999.
  • Memory Bank Disambiguation using Modulo Unrolling for Raw Machines,
    (pdf, postscript, compressed postscript)
    by Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
    Proceedings of the Fifth International Conference on High Performance Computing, Chennai, India, December 17-20, 1998.
  • Hot Pages: Software Caching for Raw Microprocessors ,
    pdf, postscript, compressed postscript)
    by Csaba Andras Moritz, Matthew Frank, Walter Lee,and Saman Amarasinghe
    MIT/LCS Technical Memo LCS-TM-599, August, 1999.
  • Software Based Instruction Caching for the RAW Architecture,
    by Jason E Miller
    Master’s Thesis, Massachusetts Institute of Technology, Cambridge, MA, May, 1999. (pdf, postscript, compressed postscript)

More Technical Reports and Papers

  • Stream Algorithms and Architecture
    (pdf , postscript)
    by Henry Hoffmann, Volker Strumpen, and Anant Agarwal.
    Laboratory for Computer Science, MIT, Technical Memo MIT-LCS-TM-636, March 2003.
  • How to build scalable on-chip ILP networks for a decentralized architecture
    (pdf)
    by Michael Taylor, Walter Lee, Matt Frank, Saman Amarasinghe, and Anant Agarwal.
    MIT/LCS Technical Memo MIT-LCS-TM-628. Submitted to ASPLOS-2000, April 2000.
  • Scalar Operand Networks: On-chip Interconnect for ILP in Partitioned Architectures,
    (pdf)
    by Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
    MIT/LCS Technical Report LCS-TR-859, July 2002
  • Design Decisions in the Implementation of a Raw Architecture Workstation,
  • (pdf)
    by Michael Bedford Taylor.
    MS Thesis, Cambridge, MA, September, 1999.

  • The Raw Processor Specification ,
  • by Michael Bedford Taylor.
    Comprehensive specification for the Raw processor, Cambridge, MA, Continuously Updated 2003. (pdf)

  • Exploring Performance-Cost Optimal Designs for Raw Microprocessors,
  • (pdf, postscript, compressed postscript)
    by C Andras Moritz, Donald Yeung, and Anant Agarwal.
    Proceedings of the International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM98, April, 1998.

  • The Raw Compiler Project,
  • (pdf, postscript, compressed postscript)
    by Anant Agarwal, Saman Amarasinghe, Rajeev Barua, Matthew Frank, Walter Lee, Vivek Sarkar, Devabhaktuni Srikrishna, and Michael Taylor.
    Proceedings of the Second SUIF Compiler Workshop, Stanford, CA, August 21-23, 1997.

  • Baring it all to Software: The Raw Machine,
  • (pdf, postscript, compressed postscript)
    by Elliot Waingold, Michael Taylor, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Srikrishna Devabhaktuni, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal.
    MIT/LCS Technical Report TR-709, March 1997.