2nd Workshop on Architecture Research using FPGA Platforms

Sunday February 12, 2006
Held in conjunction with the
12th International Symposium on High-Performance Computer Architecture (HPCA-12)
Austin, Texas

Workshop Organizers:
Arvind, MIT
Krste Asanovic, MIT
Derek Chiou, UT Austin
James Hoe, CMU
Christoforos Kozyrakis, Stanford
Shih-Lien Lu, Intel

*** Technical Program (with links to abstracts and slides) ***

*** Instructions for Presenters ***

Workshop Description

FPGAs have advanced to the point where complex microprocessors can be mapped to a single part. This provides an exciting new model for architecture research, where architectural ideas can be prototyped in great detail yet with sufficient performance to support realistic evaluation on long running applications. This workshop has the goal of advancing the field by providing a forum to share ideas and promote discussion of how to best share research infrastructure. The focus is on using FPGAs to aid in architecture research, not in the well-established areas of using FPGAs for reconfigurable computing and custom computing machines.

Previous workshop website: WARFP-2005

Call for Participation

There will be three types of presentation at the workshop.

The format of the workshop is intended to be highly interactive, with long breaks and at least two hours reserved for discussion after the presentations.

Topics of interest include:

Submission Details

Participants are invited to submit a PDF abstract of up to four pages for the talks (no denser than double column, 10 point, single-spaced). Accepted abstracts will be categorized as either regular or short talks depending on the committee's view of time required to present the contribution. Demonstration proposals are welcome either standalone or in conjunction with a talk abstract, and should be a maximum of two pages. Submissions exceeding guideline lengths will be summarily rejected.