The Virtual Wires project explores methods to overcome pin limitations in FPGA's (Field Programmable Gate Array). This can be done by multiplexing the IO signals of the FPGA. Intelligent multiplexing and pipelining of these signals to other FPGA's and devices at high frequencies yields what we call virtual wires! (for more information)
The Virtual Wires project is under the direction of Anant Agarwal and is a part of the Computer Architecture Group for the Laboratory for Computer Science at MIT.
...more to come!
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