Superword Level Parallelism

Increasing focus on multimedia applications has resulted in the addition of short SIMD instructions to most existing general-purpose microprocessors. Successful exploitation of these multimedia extensions requires compiler technology that can target them automatically. We have developed a technique based on loop unrolling and basic block vectorization that is simpler than traditional techniques, yet is capable of extracting the available parallelism.

• S. Larsen and S. Amarasinghe. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. In Proceedings of the SIGPLAN '00 Conference on Programming Language Design and Implementation, Vancouver, B.C., June 2000. (ps, pdf)
  
  • errata (correct in online version)

• Samuel Larsen. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. Master's thesis, Massachusetts Institute of Technology, May 2000. (ps, pdf)

• S. Larsen, E. Witchel, and S. Amarasinghe. Increasing and Detecting Memory Address Congruence. In Proceedings of the 11th International Conference on Parallel Architectures and Compilation Techniques, Charlottesville, VA, Sep 2002. (ps, pdf)

• PLDI '00, Vancouver, B.C., June 19, 2000 (ppt)

• PACT '02, Charlottesville, VA, 23, Sept. 2002 (ppt)

• Sam Larsen
  

• Saman Amarasinghe
  

• Vectorization in the Intel Compiler (Aart Bik)

• DIVA at ISI

• PALMS at Princeton University

• Vector compilation at the University of Toronto

• SWAR (SIMD Within A Register) at Purdue University

Industry:

• SIMDtech (AltiVec)

• SSE in the Pentium 4

• Optimizing Compilers for Modern Architectures: A Dependence-based Approach

• High Performance Compilers for Parallel Computing