Hardware Transactional Memory

In many dynamic thread-parallel applications, lock management is the source of much programming complexity as well as space and time overhead. We are investigating possible practical microarchitectures for implementing transactional memory, which provides a superior solution for atomicity that is much simpler to program than locks, and which also reduces space and time overheads.

This project is a collaboration with the Supertech group.

Publications

[1]		"Hardware Support for Unbounded Transactional Memory", Sean Lie, M.Eng. Thesis, Massachusetts Institute of Technology, May 2004. (PDF)
[2]		"Unbounded Transactional Memory", C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie, 11th International Symposium on High Performance Computer Architecture (HPCA-11), San Francisco, CA, February 2005. (PDF)

Funding

We gratefully thank the past and present sponsors of this work, including NSF, SMA, and DARPA/SGI.