The Raw project's approach to achieving these goals is to implement a simple, highly parallel VLSI architecture, and to fully expose the low-level details of the hardware architecture to the compiler so that the compiler or the software can determine, and implement, the best allocation of resources for each application. Raw is a tiled multicore architecture. It is composed of a set of interconnected tiles, each tile comprising instruction, switch-instruction, and data memory, an ALU, FPU, registers, a dynamic router, and a programmable switch.
Our approach leverages the same set of features that make application-specific custom hardware systems popular for specific applications. First, Raw implements fine-grain communication between large numbers of replicated processing elements and, thereby, is able to exploit huge amounts of fine-grain parallelism in applications, when this parallelism exists. Second, it exposes the complete details of the underlying hardware architecture to the software system (be it the software CAD system, the applications software, or the compiler), so the software can carefully orchestrate the execution of the application by applying techniques such as pipelining, synchronization and conflict elimination for shared resources by static scheduling and routing.
The Raw Prototype was implemented in collaboration with IBM using IBM's 180 nm 6-layer CU SA-27E process. We have prototypes up and running in our lab. See the Raw Picture Gallery.
Raw is funded by Darpa, NSF and the Oxygen partnership.
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