ASPLOS VII: Advance Program and Proceedings

Postscript Version of the Advance Program

Tuesday, October 1

Second NOW/Cluster Workshop: Building Systems of Systems (link to slow server)

Wednesday, October 2

Session 1: Welcome and Multiprocessors: 9:00-10:30

• The Case for a Single-Chip Multiprocessor
  Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson and Kunyung Chang: Stanford University
• An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors
  Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve and Tracy Harton: Rice University

Session 2: More Multiprocessors: 11:00-1200

• Synchronization and Communication in the T3E Multiprocessor
  Steven L. Scott: Cray Research, Inc.
• Evaluation of Architectural Support for Global Address-Based Communication in Large-Scale Parallel Machines
  Arvind Krishnamurthy: University of California at Berkeley, Klaus E. Schauser, Chris J. Scheiman: University of California at Santa Barbara, Randolph Y. Wang, David E. Culler and Katherine Yelick: University of California at Berkeley

Session 3: Threads: 1:30-2:30

• Whole-Program Optimization for Time and Space Efficient Threads
  Dirk Grunwald: University of Colorado at Boulder and Richard Neves: IBM T.J. Watson Research Center
• Thread Scheduling for Cache Locality
  James Philbin, Jan Edler: NEC Research Institute, Otto J. Anshus: University of Tromso, Craig C. Douglas: IBM T.J. Watson Research Center and Kai Li: Princeton University

Session 4: File and Storage Systems: 3:00-4:00

• The Rio File Cache: Surviving Operating System Crashes
  Peter M. Chen, Wee Teck Ng, Subhachandra Chandra, Christopher Aycock, Gurushankar Rajamani and David Lowell: University of Michigan
• Petal: Distributed Virtual Disks
  Edward K. Lee and Chandramohan A. Thekkath: Digital SRC

Session 5: Memory Requirements: 4:30-5:30

• A Quantitative Analysis of Loop Nest Locality
  Kathryn S. McKinley: University of Massachusetts and Olivier Temam: Versailles University
• The Intrinsic Bandwidth Requirements of Ordinary Programs
  Andrew S. Huang and John Paul Shen: Carnegie Mellon University

Thursday, October 3

Session 6: Value and Branch Prediction: 9:00-10:30

• Multiple-Block Ahead Branch Predictors
  Andre Seznec: IRISA, Stephan Jourdan, Pascal Sainrat: IRIT and Pierre Michaud: IRISA
• Analysis of Branch Prediction Via Data Compression
  I-Cheng K. Chen, John T. Coffey and Trevor N. Mudge: University of Michigan
• Value Locality and Load Value Prediction
  Mikko H. Lipasti, Christopher B. Wilkerson and John Paul Shen: Carnegie Mellon University

Session 7: Potpourri: 11:00-12:00

• The Structure and Performance of Interpreters
  Theodore H. Romer, Dennis Lee, Geoffrey M. Voelker, Alec Wolman, Wayne A. Wong, Jean-Loup Baer, Brian N. Bershad and Henry M. Levy: University of Washington
• Adapting to Network and Client Variability via On-Demand Dynamic Distillation
  Armando Fox, Steven D. Gribble, Eric A. Brewer and Elan Amir: University of California at Berkeley Paper also available in pdf

Session 8: Work-in-Progress: 1:30-3:00

• Submission guidelines

Session 9: Distributed Shared Memory: 3:30-5:30

• Shasta: A Low Overhead, Software-Only Approach for Supporting Fine-Grain Shared Memory
  Daniel J. Scales, Kourosh Gharachorloo: Digital WRL and Chandramohan A. Thekkath: Digital SRC
• An Integrated Compile-Time/Run-Time Software Distributed Shared Memory System
  Sandhya Dwarkadas, Alan L. Cox and Willy Zwaenepoel: Rice University
• Hiding Communication Latency and Coherence Overhead in Software DSMs
  R. Bianchini: Federal University of Rio de Janeiro, L. I. Kontothanassis: University of Rochester, R. Pinto, M. De Maria, M. Abud and C. L. Amorim: Federal University of Rio de Janeiro
• SoftFLASH: Analyzing the Performance of Clustered Distributed Virtual Shared Memory
  Andrew Erlichson: Stanford University, Neal Nuckolls, Greg Chesson: Silicon Graphics, Inc. and John Hennessy: Stanford University

Panel Discussion: Thursday 8-10 PM

"How to compute with a billion transistors on a chip"

Our opinionated, fun, and visionary panelists will argue about the "right way" to do so, probably covering multithreading, status quo, super speculation, simultaneous multithreading, on-chip multiprocessors, reconfigurable computing, processors in memory, and abacuses on a chip. Panelists include:
• Tom Knight, MIT
• Hank Levy, University of Washington
• John Moussouris, formerly of Microunity, Inc.
• Bob Parker, DARPA
• David Patterson, University of California, Berkeley
• Kunle Olukotun, Stanford
• Guri Sohi, University of Wisconsin
• Moderator: Anant Agarwal, MIT

Friday, October 4

Session 10: Compiler Optimizations: 9:00-10:30

• Compiler-Based Prefetching for Recursive Data Structures
  Chi-Keung Luk and Todd C. Mowry: University of Toronto
• Exploiting Dual Data-Memory Banks in Digital Signal Processors
  Mazen A. R. Saghir, Paul Chow and Corinna G. Lee: University of Toronto
• Compiler-Directed Page Coloring for Multiprocessors
  Edouard Bugnion, Jennifer M. Anderson: Stanford University, Todd C. Mowry: University of Toronto, Mendel Rosenblum and Monica S. Lam: Stanford University

Session 11: Caches and Memory Systems 11:00-12:30

• Reducing Network Latency Using Subpages in a Global Memory Environment
  Herve A. Jamrozik, Michael J. Feeley, Geoffrey M. Voelker, James Evans II, Anna R. Karlin, Henry M. Levy and Mary K. Vernon: University of Washington
• Improving Cache Performance with Balanced Tag and Data Paths
  Jih-Kwon Peir: University of Florida, Windsor W. Hsu: University of California at Berkeley, Honesty Young and Shauchi Ong: IBM Almaden Research Center
• Operating System Support for Improving Data Locality on CC-NUMA Compute Servers
  Ben Verghese, Scott Devine, Anoop Gupta and Mendel Rosenblum: Stanford University

Saturday, October 5

Sixth Workshop on Scalable Share Memory Multiprocessors