Chaiken. Cache Coherence Protocols for Large-Scale
Multiprocessors. Master's thesis, Massachusetts Institute of
Technology, Department of Electrical Engineering and Computer Science,
September 1990. Also available as MIT/LCS Technical Report
(pdf, compressed postscript)
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both average memory access latency and network traffic. However, cache-based systems must address the problem of cache coherence. This thesis presents the results of the search for a cache coherence protocol for Alewife, a large-scale multiprocessor being built at MIT. The research focuses on protocols that use a directory, a list of cached copies of data, to avoid the need for a system-wide broadcast mechanism. Both trace-driven and execution-driven simulation techniques are used to compare various coherence schemes. In addition to evaluating the protocols in terms of hardware overhead and performance, the thesis reports on the experience gained by implementing several different schemes in ASIM, the Alewife machine simulator. The protocol search reaches two major conclusions: First, by using system-level optmizations, it is possible to use caches to build large-scale shared-memory multiprocessors. Second, the Alewife machine should use the integrated systems approach --- handling common cases in hardware and exceptional cases in software --- to solve the cache coherence problem.
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