MIT Alewife Project: Home Page

Alewife is a large-scale multiprocessor that integrates both cache-coherent, distributed shared memory and user-level message-passing in a single integrated hardware framework. Each Alewife node consists of a 33 MHz Sparcle integer unit, an off-the-shelf FPU, 64 kbytes of direct-mapped cache, and 4 Mbytes of globally-shared main memory. The nodes communicate via messages on a two-dimensional mesh network. The current implementation scales directly to 512 nodes.

A single-chip Communication and Memory Management Unit (CMMU) on each node holds the cache tags and implements the memory coherence protocol by synthesizing messages to other nodes. All of the node components have been fabricated and tested. Currently, there are three working Alewife machines: one 32-processor system and two four-processor systems. We also have complete packaging for a 128-node system that will be populated with Alewife nodes in the near future. (The 32-node system resides in the lower right quarter of the 128-node chassis.)

In addition to our hardware efforts, the Alewife group is pursuing a number of software issues, including synchronization, compilation, runtime-systems and operating-systems design. We currently support two languages, C and MUL-T (a multithreaded dialect of scheme with futures).

The Alewife project is funded in part by ARPA contract N00014-94-1-0985, in part by NSF Experimental Systems grant MIP-9012773, and in part by an NSF Presidential Young Investigator Award.

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$Date: 2009/03/12 14:03:46 $